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CD4017 Frequency Divider IC (again...)

I ran into a problem when testing (playing with) the 555 square wave signal generator. If I use small values for the capacitors (<100pf) and resistors (<2k), then the timer frequencies rise and I have a lot of trouble checking the output of the generator with my cheap DSO138 oscilloscope (limit 200kHz). The signal looks like it degrades and then disappears from about 50kHz onwards.

Mmmm...not much of a "square" wave at 50kHz

Yep, and all squares gone at 150kHz

I wanted to know if the obvious signal degradation at higher frequencies was a function of the oscilloscope or the signal generator itself, so I needed a way to "slow" the signal up to measure - like an electronic gear system.

When searching online for solutions ("NO to a $500 oscilloscope!", says the budget-master) I found a couple of references to using a CD4017 decade counter. I have used this chip before and blogged about it already when I made a stupid clap switch circuit.

In some configurations this chip is capable of frequency division, for example taking a clock input of 100Hz and dividing it by two to output 50Hz. It can maximum divide by a factor of 10 (pin 15 tied to ground), so I thought that at least I could "down shift" the signal by this amount and maybe get more sense from the oscilloscope.

In the CD4017 datasheet there is actually a hint that you can "cascade" the counters and thus continue dividing by 10. So if I can link three such chips correctly, I could now lower the frequency by a factor of 10x10x10=1000, so a dodgy signal at 50kHz=50000Hz might perhaps be readable by my dumb 'scope at 50Hz.

The cascade shown in the datasheet seems like an overly complicated circuit with overflows, AND gates, etc. I thought that maybe all I really need to do is pump a signal from one CD4017 (divided by 10) into the input of the next chip as per the following circuit diagram.

The yellow wire is the signal from the 555 generator to pin 14 (clock, indicated with a blue LED), then each chip is powered by a red wire from VCC. Blue is GND, grey from GND to pin 13 (clock inhibit) will make the counter advance one at the positive edge of the clock signal. Orange from pin 15 (reset) tied to ground makes the IC divide by 10.

Finally, white from chip 1 (pin2 - output) to chip 2 (pin 14 - clock) and from chip 2 (pin 2 - output) to chip 3 (pin 14 - clock) provides each cascaded chip with the divided by 10 signal from the previous chip. I will test this version of a cascading signal divider with a lower frequency first, and then ramp it up and see what's happening at the higher frequencies.

I have a strong suspicion at the end of this investigation that the lovely square wave we can see on the screen at these higher frequencies is a result of monitoring the output of the CD4017 IC, which squares the signal off nicely, even if you feed it a sine wave (see the video). Maybe the signal generator output is genuinely "messy" at higher frequencies? 

So I guess to resolve this remaining question I will need to start campaigning to higher powers to fund a proper oscilloscope so that I can measure the direct output!

In the meantime with the help of the CD4017 I can output a clean square wave at high frequencies from the 555 timer (indeed an opAmp or comparator would also be a solution to "squaring off" a messy signal). It is nice to know that I can make a fit for purpose clock signal - I think I'll feed it to an Attiny85 as an external clock just for fun at some stage.